This invention relates to an optical disk apparatus for reproducing data recorded on an optical disk such as a DVD (Digital Versatile Disk) or DVDVRAM or recording data thereon.
Recently, DVDs or DVDRAMs have been developed as an optical recording medium of large capacity. This type of optical disk can be used to record a large amount of data with high density and correctly reproduce recorded data. To serve the purpose, record data and an error correction code used for correcting an error of the recorded data are recorded on the optical disk.
A method for recording data on this type of optical disk is explained with reference to FIGS. 3A to 3D. As is clearly seen from FIG. 3B showing the enlarged recording surface of part of an optical disk 10 shown in FIG. 3A, a plurality of pits 11 are formed. Sets of the pits 11 constitute sectors as shown in FIGS. 3C, 3D. For example, a track (not shown) is formed in a spiral form from the center towards the periphery on the surface of the optical disk 10 and a sector string formed of a plurality of sectors is formed on the track. The sector string is continuously read by an optical head and recorded data is reproduced on the real time basis.
FIGS. 4A, 4B show a sector in which data is recorded. One sector is constructed by 13 rows.times.2 frames and sync. codes SY0, . . . , SY7 are attached to the frames. The sync. code is used to define a reference timing of a serial/parallel conversion circuit which will be described later. In FIG. 4B, the frame arrangement is shown in a 2-dimensional form, but the frames are recorded in order on the track starting from the top frame. That is, if the frames are shown in an order of the sync. codes, the frames are arranged on the track in an order of SY0, ST5, SY1, SY5, SY2, SY5, . . . . The order of each frame can be recognized from the relation between the two continuous sync. codes. The number of bits of the sync. codes constituting one frame is 32 bits (=16 bits.times.2) and the number of bits of data is 1456 bits (=16 bits.times.91). The equations in the parentheses indicate that the sync. code and data are 16-bit modulation codes. That is, when data is recorded on the optical disk, 8-bit data is modulated into 16-bit data.
FIG. 5A shows one decoded sector. In the recording sector, 16-bit data in the above sector is decoded into 8 bits. The data amount in the recording sector is (172+10) bytes.times.(12+1) rows. In each row, a 10-byte error correction code is added. Further, an error correction code of one row is present in the sector and the error correction code functions as an error correction code for the column direction when 12 rows are obtained as will be described later.
FIG. 5B shows a data block in which the error correction code is removed from the data of one sector shown in FIG. 5A. The data block has a sector ID (4 bytes) for identifying a sector, an ID error detection code IED (2 bytes) for detecting an error of the sector ID and copyright management information CPR-MAI (6 bytes) which are attached to the head portion of 2048-byte main data and an error detection code EDC (4 bytes) attached to the end portion of the data.
Next, the error correction code block (ECC block) is explained.
The ECC block shown in FIGS. 6, 7 is constructed by 16 sectors having the same construction as described above. However, the sync. code is eliminated. As shown in FIG. 6, a 16-byte outer parity (PO) is attached to each column and a 10-byte inner parity (PI) is attached to each row. The outer parity (PO) is error correction data of 172 columns and the inner parity (PI) is error correction data of (192+16) rows. As shown in FIG. 7, at the time of recording, the outer parity (PO) of 16 rows shown in FIG. 6 is arranged in a distributed manner in one sector for each row. As a result, one recording sector is constructed as data of 13 (=12+1) rows. In FIG. 6, B0, 0, B0, 1, . . . each indicate an address of byte unit. Further, in FIG. 7, numerals 0 to 15 attached to the sectors indicate the numbers of the recording sectors.
FIG. 8 shows the relation between one row of the ECC block shown in FIG. 6 and the frames included in the sector. The ECC block of one row (172 bytes+10 bytes=182 bytes) corresponds to two frames (1456 bits+1456 bits=91 bytes+91 bytes=182 bytes) obtained by eliminating the sync. code in the sector.
FIG. 9 shows a disk apparatus related to this invention. A disk motor 201 drives and rotates an optical disk 202. An optical head, for example, a laser pickup 203 applies a beam to the pit string on the optical disk 202 to detect the reflected beam by use of a built-in photodiode (not shown) or the like and convert the detected beam into an electrical signal (high-frequency signal: RF signal). An RF amplifier 204 amplifies an RF signal output from the laser pickup 203 and subjects the amplified RF signal to the waveform equalization process. Further, the RF amplifier 204 creates and outputs a focus error signal 205 and tracking error signal 206. A servo control circuit 207 compensates for the gains and phases of the focus error signal 205 and tracking error signal 206 output from the RF amplifier 204 to drive an actuator (not shown) in the laser pickup 203. Thus, the stable focus servo and tracking servo can be effected.
A slicer 208 binary-codes an RF signal output from the RF amplifier 204 into a 1-bit digital signal. A data PLL (Phase Locked Loop) circuit 209 reproduces a bit clock signal 210 in synchronism with the RF signal supplied from the slicer 208. A serial/parallel (S/P: Serial/Parallel) conversion circuit 211 serial/parallel-converts the 1-bit RF signal supplied from the slicer 208 in the unit of 16 bits. As described before, the S/P conversion timing signal is created based on the sync. code in the DVD signal. That is, a sync. code detection circuit 212 detects a sync. code (SY0 to SY7) shown in FIG. 4B from the binary-coded RF signal supplied from the slicer 208. A frame counter 213 counts (32+1456) bits in one frame in synchronism with the sync. code supplied from the sync. code detection circuit 212. A timing signal generating circuit 214 generates a timing signal for the S/P conversion circuit 211 or the like based on the count of the frame counter 213. An 8/16 demodulation circuit 215 converts a 16-bit code supplied from the S/P conversion circuit 211 into 8-bit data. The converting operation is effected according to conversion data stored in a ROM 216.
A frame number detection circuit 217 fetches sync. codes of several frames supplied from the sync. code detection circuit 212 and detects the present frame number based on the relation between the preceding and succeeding sync. codes. A frame number counter 219 loads and corrects the frame number supplied from the frame number detection circuit 217.
An ID detection circuit 220 detects an sector ID provided in the sector unit shown in FIG. 5B. An address generating circuit 221 generates an address used when data output from the 8/16 demodulation circuit 215 is written into a RAM 222 based on the output signal of the frame number counter 219 and the output signal of the ID detection circuit 220. The 8-bit data output from the 8/16 demodulation circuit 215 is supplied to the RAM 222 via a data bus 223 and written into an area corresponding to the address generated from the address generating circuit 221.
An error correction circuit 224 corrects data stored into the RAM 222 in the unit of inner parity PI and outer parity PO shown in FIG. 6. A CPU 225 controls the operation of the whole portion of the optical disk apparatus. An input/output I/F (Inter Face) circuit 226 controls the input/output of data between the RAM 222 and an external device (not shown).
As described before, the sync. codes attached to the frames of the sector are periodically arranged and the order of the frames can be recognized according to the order of the sync. codes. Therefore, if the periodicity of the sync. codes is disturbed, data processed in the S/P conversion circuit 211 and the frame number now counted by the frame number counter 219 become different from each other and the address of the RAM in which data is finally written becomes different. In order to prevent the problem, for example, an out-of-sync. detection circuit 230 detects the out-of-sync. state based on the periodicity of the sync. codes supplied from the sync. code detection circuit 212 and outputs an out-of-sync. signal if the periodicity of the sync. codes is disturbed. The out-of-sync. detecting operation is effected in the unit of one frame, and if the synchronization is not obtained, an out-of-sync. signal is output in the unit of one frame. The out-of-sync. signal is supplied to the frame number counter 219 as a control signal for correcting the frame number counter 219. The frame number counter 219 fetches a frame number from the frame number detection circuit 217 according to the supplied control signal and corrects the frame number.
As is explained with reference to FIG. 8, one row including the inner parity PI of the ECC block is constructed by data of two frames except the sync. code of the sector in the physical sector shown in FIG. 4B. However, the control signal for counter correction from the out-of-sync. detection circuit 230 shown in FIG. 9 is output in the unit of one frame and the frame number counter 219 corrects the frame number in the unit of one frame. For this reason, if the continuity between the two frames constituting one row of the ECC block is disturbed, there occurs a possibility that one row is constructed by two frames having no relation with each other from the viewpoint of data correction. Thus, the correction ability of the error correction circuit 224 is lowered if the continuity between the two frames constituting one row of the ECC block is disturbed.